PIC18F1230T-I/SO【PDF 152/318 页】IC PIC MCU FLASH 2KX16 18SOIC

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Sheet目录3871

148页 149页 150页 151页 [152页]153页 154页 155页 156页

PIC18F1230/1330

2009 Microchip Technology Inc.

DS39758D-page 235

DECFSZ

Decrement f, Skip if 0

Syntax:

DECFSZ f {,d {,a}}

Operands:

0

f 255

d

[0,1]

a

[0,1]

Operation:

(f) – 1

dest,

skip if result = 0

Status Affected:

None

Encoding:

0010

11da

ffff

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode”

for details.

Words:

1

Cycles:

1(2)

Note:

3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

If skip:

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

Example:

HERE

DECFSZ

CNT, 1, 1

GOTO

LOOP

CONTINUE

Before Instruction

PC

=

Address (HERE)

After Instruction

CNT

=

CNT – 1

If CNT

=

0;

PC =

Address (CONTINUE)

If CNT

0;

PC =

Address (HERE + 2)

DCFSNZ

Decrement f, Skip if Not 0

Syntax:

DCFSNZ

f {,d {,a}}

Operands:

0

f 255

d

[0,1]

a

[0,1]

Operation:

(f) – 1

dest,

skip if result

0

Status Affected:

None

Encoding:

0100

11da

ffff

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode”

for details.

Words:

1

Cycles:

1(2)

Note:

3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

If skip:

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

Example:

HERE

DCFSNZ

TEMP, 1, 0

ZERO

:

NZERO

:

Before Instruction

TEMP

=

?

After Instruction

TEMP

=

TEMP – 1

If TEMP

=

0;

PC

=

Address (ZERO)

If TEMP

0;

PC

=

Address (NZERO)

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